Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS
R01UH0042EJ0500 Rev.5.00 Page 47 of 1513
Aug 12, 2011
2.2 Pin States
The operation states of pins in the various operation modes are described below.
Table 2-2. Pin Operation States in Various Modes
Pin Name
When Power
Is Turned
On
Note 1
During
Reset
(Other than
When Power
Is Turned
On)
HALT
Mode
Note 2
IDLE1,
IDLE2,
Sub-IDLE
Mode
Note 2
STOP
Mode
Note 2
Idle State
Note
3
Bus Hold
DRST Pull down
Pull down
Note
4
Held Held Held Held Held
P10/ANO0, P11/ANO1 Undefined Hi-Z Held Held Hi-Z Held Held
AD0 to AD15 Notes 6, 7
A0 to A15
Undefined
Notes
6, 8
A16 to A21
Undefined
Note
6
Hi-Z Hi-Z Held Hi-Z
WAIT
− − − − −
CLKOUT Operating L L Operating Operating
WR0, WR1
RD
ASTB
H
Note 6
Hi-Z
HLDAK
H H H
L
HLDRQ
Hi-Z
Note 5
Hi-Z
Note 5
Operating
Note
6
− − −
Operating
Other port pins Hi-Z Hi-Z Held Held Held Held Held
Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit)
when the power is turned on.
2. Operates while alternate functions are operating.
3. The state of the pins in the idle state inserted after the T3 state is shown.
4. Pulled down during external reset. During internal reset by the watchdog timer or clock monitor, etc., the state
of this pin differs according to the OCDM.OCDM0 bit setting.
5. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode).
6. Operates even in the HALT mode, during DMA operation.
7. In separate bus mode: Hi-Z
In multiplexed bus mode: Undefined
8. In separate bus mode
Remark Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L: Low-level output
H: High-level output
−: Input without sampling (not acknowledged)