Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 469 of 1513
Aug 12, 2011
9.6.1 Interval timer mode (TT0MD3 to TT0MD0 bits = 0000)
In the interval timer mode, an interrupt request signal (INTTT0CC0) is generated at the interval set by the TT0CCR0
register if the TT0CTL0.TT0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from
the TOT00 pin.
The TT0CCR1 register is not used in the interval timer mode. However, the set value of the TT0CCR1 register is
transferred to the CCR1 buffer register, and when the count value of the 16-bit counter matches the value of the CCR1
buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. In addition, a square wave, which is
inverted when the INTTT0CC1 signal is generated, can be output from the TOT01 pin.
The value of the TT0CCR0 and TT0CCR1 registers can be rewritten even while the timer is operating.
Figure 9-7. Configuration of Interval Timer
16-bit counter
Output
controller
CCR0 buffer registerTT0CE bit
TT0CCR0 register
Count clock
selection
Clear
Match signal
TOT00 pin
INTTT0CC0 signal
Figure 9-8. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
TOT00 pin output
INTTT0CC0 signal
D 0
D 0 D 0 D 0 D 0
Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1)