Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 468 of 1513

Aug 12, 2011

Figure 9-6. Timing of Batch Write

0000H D

TT0CE bit = 1

Note 1

16-bit counter

TT0CCR0 register

TT0CCR1 register

INTTT0CC0 signal

INTTT0CC1 signal

TOT01 pin output

TOT00 pin output

CCR0 buffer register

CCR1 buffer register

Note 1

Same value write

0000H

Note 2 Note 3

FFFFH

Notes 1. Because the TT0CCR1 register was not rewritten, D

03 is not transferred.

2. Because the TT0CCR1 register has been written (D

12), data is transferred to the CCR1

buffer register upon a match between the value of the 16-bit counter and the value of the

TT0CCR0 register (D

01).

3. Because the TT0CCR1 register has been written (D

12), data is transferred to the CCR1

buffer register upon a match between the value of the 16-bit counter and the value of the

TT0CCR0 register (D

02).

Remarks 1. D

01, D02, D03: Set values of TT0CCR0 register

11, D12: Set values of TT0CCR1 register

2. The above timing chart illustrates the operation in the PWM output mode as an example.