Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 466 of 1513
Aug 12, 2011
(b) Batch write
In this mode, data is transferred all at once from the TT0CCR0 and TT0CCR1 registers to the CCR0 and CCR1
buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0
buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TT0CCR1 register.
Whether to enable or disable the next transfer timing is controlled by writing or not writing to the TT0CCR1
register.
In order for the set value when the TT0CCR0 and TT0CCR1 registers are rewritten to become the 16-bit
counter comparison value (in other words, in order for this value to be transferred to the CCR0 and CCR1
buffer registers), it is necessary to rewrite the TT0CCR0 register and then write to the TT0CCR1 register before
the 16-bit counter value and the CCR0 buffer register value match. Therefore, the values of the TT0CCR0 and
TT0CCR1 registers are transferred to the CCR0 and CCR1 buffer registers upon a match between the count
value of the 16-bit counter and the value of the CCR0 buffer register. Thus even when wishing only to rewrite
the value of the TT0CCR0 register, also write the same value (same as preset value of the TT0CCR1 register)
to the TT0CCR1 register.