Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 463 of 1513
Aug 12, 2011
(d) Count value hold operation
The value of the 16-bit counter is held by the TT0CTL2.TT0ECC bit in the encoder compare mode. The value
of the 16-bit counter is reset to FFFFH when the TT0ECC bit = 0 and TT0CTL0.TT0CE bit = 0. When the
TT0CE bit is next set to 1, the set value of the TT0TCW register is transferred to the 16-bit counter and a count
operation is performed.
If the TT0ECC bit = 1 and TT0CE bit = 0, the value of the 16-bit counter is held. When the TT0CE bit is next
set to 1, the counter resumes the count operation from the held value.
(e) Counter read operation during count operation
The value of the 16-bit counter of TMT0 can be read by using the TT0CNT register during the count operation.
When the TT0CTL0.TT0CE bit = 1, the value of the 16-bit counter can be read by reading the TT0CNT register.
If the TT0CNT register is read when the TT0CTL2.TT0ECC bit = 0 and TT0CE bit = 0, however, it is 0000H.
The held value of the TT0CNT register is read if the register is read when the TT0ECC bit = 1 and TT0CE bit =
0.
(f) Underflow operation
A 16-bit counter underflow occurs at the timing when the 16-bit counter value changes from 0000H to FFFFH
in the encoder compare mode. When an underflow occurs, the TT0OPT1.TT0EUF bit is set to 1 and an
interrupt request signal (INTTT0OV) is generated.
(g) Interrupt operation
TMT0 generates the following four types of interrupt request signals.
• INTTT0CC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer register
and as a capture interrupt request signal to the TT0CCR0 register.
• INTTT0CC1 interrupt: This signal functions as a match interrupt request signal of the CCR1 buffer register
and as a capture interrupt request signal to the TT0CCR1 register.
• INTTT0OV interrupt: This signal functions as an overflow interrupt request signal.
• INTTT0EC interrupt: This signal functions as a valid edge detection interrupt request signal of the
encoder clear input (TECR0 pin).