Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 459 of 1513
Aug 12, 2011
A timing example of noise elimination performed by the timer T input pin digital filter is shown Figure 9-2.
Figure 9-2. Example of Digital Noise Elimination Timing
Noise elimination clock
Input signal
Internal signal
3 clocks
Sampling
3 times
3 clocks 1 clock 1 clock 2 clocks 2 clocks
Sampling
3 times
Remark If there are two or fewer noise elimination clocks while the TIT00, TIT01, TENC01, TECR0, and
EVTT00 input signals are high level (or low level), the input signal is eliminated as noise. If it is
sampled three times or more, the edge is detected as a valid input.