Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 458 of 1513
Aug 12, 2011
(14) Noise elimination control register (TTNFC)
Digital noise elimination can be selected for the TIT00, TIT01, TENC01, TECR0, and EVTT00 pins. The noise
elimination settings are performed using the TTNFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f
XX,
fXX/4, fXX/8, fXX/16, fXX/32, and fXX/64. Sampling is performed 3 times.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution Time equal to the sampling clock × 3 clocks is required until the digital noise eliminator is
initialized after the sampling clock has been changed. If the valid edge of the TIT00, TIT01,
TENC01, TECR0, and EVTT00 pins is input after the sampling clock has been changed and
before the time of the sampling clock × 3 clocks passes, therefore, an interrupt request signal
may be generated. Therefore, when using the external trigger function, the external event
function, the capture trigger function, and the encoder function of TMT, enable TMT operation
after the sampling clock × 3 clocks have elapsed.
TTNFENTTNFC 0 0 0 0 TTNFC2 TTNFC1 TTNFC0
f XX
f XX /4
f
XX /8
f
XX /16
f
XX /32
f
XX /64
TTNFC2
0
0
0
0
1
1
Digital sampling clock
Setting prohibited
TTNFC1
0
0
1
1
0
0
TTNFC0
0
1
0
1
0
1
After reset: 00H R/W Address: FFFFF726H
Digital noise elimination not executed
Digital noise elimination executed
TTNFEN
0
1
Settings of digital noise elimination
Other than above
Remarks 1. Since sampling is performed three times, the noise width for reliably
eliminating noise is 2 sampling clocks.
2. In the case of noise with a width smaller than 2 sampling clocks, an
interrupt request signal is generated if noise synchronized with the
sampling clock is input.