Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 452 of 1513

Aug 12, 2011

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TT0ESF

TMT0 count-up/-down operation status detection flag

• This bit is cleared to 0 if the TT0CTL0.TT0CE bit = 0 when the

TT0CTL2.TT0ECC bit = 0.

• The status of the TT0ESF bit is retained even if the TT0CE bit = 0 when the

TT0ECC bit = 1.

TMT0 is counting up.

TMT0 is counting down.

TT0EOF

Set (1)

Reset (0)

Overflow detection flag for TMT0 encoder function

• The TT0EOF bit is set to 1 when the 16-bit counter overflows from FFFFH to

0000H in the encoder compare mode.

• As soon as the TT0EOF bit has been set to 1, an overflow interrupt request signal

(INTTTOV0) is generated. At this time, the TT0OPT0.TT0OVF bit is not set to 1.

• The TT0EOF bit is not cleared to 0 even if the TT0EOF bit or TT0OPT1 register

is read when the TT0EOF bit = 1.

• The status of the TT0EOF bit is retained even if the TT0CTL0.TT0CE bit is cleared

to 0 when the TT0CTL2.TT0ECC bit = 1.

• Before clearing the TT0EOF bit to 0 after the INTTTOV0 signal is generated, be

sure to confirm (read) that the TT0EOF bit is set to 1.

• The TT0EOF bit can be read or written, but it cannot be set to 1 by software.

Writing 1 to this bit does not affect the operation of TMT0.

Overflow occurs.

Cleared by writing 0 to the TT0EOF bit or when the TT0CTL0.TT0CE

bit = 0

Caution Be sure to set bits 3 to 7 to “0”.