Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 451 of 1513
Aug 12, 2011
(9) TMT0 option register 1 (TT0OPT1)
The TT0OPT1 register is an 8-bit register that detects overflows, underflows, and count-up/down operations of the
encoder count function.
The TT0OPT1 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
This register can be rewritten even when the TT0CTL0.TT0CE bit = 1.
(1/2)
0TT0OPT1 0 0 0 0 TT0EUF TT0EOF TT0ESF
6 5 4 3 <2> <1>
After reset: 00H R/W Address: FFFFF608H
TT0EUF
Set (1)
Reset (0)
TMT0 underflow detection flag
• The TT0EUF bit is set to 1 when the 16-bit counter underflows from 0000H to
FFFFH in the encoder compare mode.
• When the TT0CTL2.TT0LDE bit = 1, the TT0EUF bit is set to 1 when the value of
the 16-bit counter is changed from 0000H to the set value of the TT0CCR0 register.
• An overflow interrupt request signal (INTTTOV0) is generated as soon as the
TT0EUF bit is set to 1.
• The TT0EUF bit is not cleared to 0 even if the TT0EUF bit or TT0OPT1 register
is read when the TT0EUF bit = 1.
• The status of the TT0EUF bit is retained even if the TT0CTL0.TT0CE bit is cleared
to 0 when the TT0CTL2.TT0ECC bit = 1.
• Before clearing the TT0EUF bit to 0 after the INTTTOV0 signal is generated, be
sure to confirm (read) that the TT0EUF bit is set to 1.
• The TT0EUF bit can be read or written, but it cannot be set to 1 by software.
Setting this bit to 1 does not affect the operation of TMT0.
Underflow occurs.
Cleared by writing to TT0EUF bit or when TT0CTL0.TT0CE bit = 0
7 <0>