Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 449 of 1513
Aug 12, 2011
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TT0ECS1
0
0
1
1
TT0ECS0
0
1
0
1
Valid edge setting of encoder clear signal (TECR0 pin)
Detects no edge (clearing encoder is invalid).
Detects rising edge.
Detects falling edge.
Detects both edges.
TT0EIS1
0
0
1
1
TT0EIS0
0
1
0
1
Valid edge setting of encoder input signals (TENC00, TENC01 pins)
Detects no edge (inputting encoder is invalid).
Detects rising edge.
Detects falling edge.
Detects both edges.
Cautions 1. Rewrite the TT0SCE, TT0ZCL, TT0BCL, TT0ACL, TT0ECS1, TT0ECS0,
TT0EIS1, and TT0EIS0 bits when the TT0CTL0.TT0CE bit = 0. (The same
value can be written to these bits when the TT0CE bit = 1.) If rewriting was
mistakenly performed, clear the TT0CE bit to 0 and then set these bits
again.
2. The TT0ECS1 and TT0ECS0 bits are valid only when the TT0SCE bit = 0
and the encoder compare mode is set.
3. The TT0EIS1 and TT0EIS0 bits are valid only when the TT0CTL2.TT0UDS1
and TT0CTL2.TT0UDS0 bits = 00 or 01.