Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 448 of 1513
Aug 12, 2011
(7) TMT0 I/O control register 3 (TT0IOC3)
The TT0IOC3 register is an 8-bit register that controls the encoder clear function operation.
The TT0IOC3 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
TT0SCETT0IOC3 TT0ZCL TT0BCL TT0ACL TT0ECS1 TT0ECS0 TT0EIS1 TT0EIS0
654321
After reset: 00H R/W Address: FFFFF606H
7 0
TT0SCE
0
1
Encoder clear selection
• Clears the 16-bit counter to 0000H when the valid edge of TECR0 pin specified by
the TT0ECS1 and TT0ECS0 bits is detected when the TT0SCE bit = 0.
• Clears the 16-bit counter to 0000H when the clear level conditions of the TT0ZCL,
TT0BCL, and TT0ACL bits match the input levels of the TECR0, TENC01, and
TENC00 pins when TT0SCE bit = 1.
• Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is valid and that of the
TT0ECS1 and TT0ECS0 bits is invalid when the TT0SCE bit = 1.
An encoder clear interrupt request signal (INTTTI0EC) is not generated.
• Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is invalid and setting of
the TT0ECS1 and TT0ECS0 bits is valid when the TT0SCE bit = 0.
The INTTTI0EC signal is generated when the valid edge specified by the TT0ECS1
and TT0ECS0 bits is detected.
• Be sure to set the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits to 10 or 11
when the TT0SCE bit = 1.
Operation is not guaranteed if the TT0UDS1 and TT0UDS0 bits = 00 or 01 and
the TT0SCE bit = 1.
Clears 16-bit counter on detection of edge of encoder clear signal (TECR0 pin).
Clears 16-bit counter on detection of clear level condition of the TENC00,
TENC01, and TECR0 pins.
TT0ZCL
0
1
Clear level selection of encoder clear signal (TECR0 pin)
Setting of the TT0ZCL bit is valid only when the TT0SCE bit = 1.
Clears low level of the TECR0 pin.
Clears high level of the TECR0
pin.
TT0BCL
0
1
Clear level selection of encoder input signal (TENC01 pin)
Setting of the TT0BCL bit is valid only when the TT0SCE bit = 1.
Clears low level of the TENC01 pin.
Clears high level of the TENC01
pin.
TT0ACL
0
1
Clear level selection of encoder input signal (TENC00 pin)
Setting of the TT0ACL bit is valid only when the TT0SCE bit = 1.
Clears low level of the TENC00 pin.
Clears high level of the TENC00
pin.