Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 446 of 1513
Aug 12, 2011
(5) TMT0 I/O control register 1 (TT0IOC1)
The TT0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIT00,
TIT01 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TT0IS3
0
0
1
1
TT0IS2
0
1
0
1
Capture trigger input signal (TIT01 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
0 0 0 TT0IS3 TT0IS2 TT0IS1 TT0IS0
654321
TT0IS1
0
0
1
1
TT0IS0
0
1
0
1
Capture trigger input signal (TIT00 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
7 0
TT0IOC1
After reset: 00H R/W Address: FFFFF604H
Cautions 1. Rewrite the TT0IS3 to TT0IS0 bits when the TT0CTL0.TT0CE bit = 0.
(The same value can be written when the TT0CE bit = 1.) If rewriting
was mistakenly performed, clear the TT0CE bit to 0 and then set the
bits again.
2. The TT0IS3 and TT0IS2 bits are valid only in the free-running timer
mode (only when the TT0OPT0.TT0CCS1 bit = 1) and the pulse width
measurement mode. In all other modes, a capture operation is not
performed.
The TT0IS1 and TT0IS0 bits are valid only in the free-running timer
mode (only when the TT0OPT0. TT0CCS0 bit = 1) and the pulse width
measurement mode. In all other modes, a capture operation is not
performed.