Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 442 of 1513
Aug 12, 2011
(3) TMT0 control register 2 (TT0CTL2)
The TT0CTL2 register is an 8-bit register that controls the encoder count function operation.
The TT0CTL2 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution For details of each bit of the TT0CTL2 register, see 9.6.9 (5) Controlling bits of TT0CTL2 register.
(1/2)
TT0ECCTT0CTL2 0 0 TT0LDE TT0ECM1 TT0ECM0 TT0UDS1 TT0UDS0
654321
Disables transfer of set value of TT0CCR0 to 16-bit counter in case of underflow.
Enables transfer of set value of TT0CCR0 to 16-bit counter in case of underflow.
TT0LDE
0
1
Transfer setting to 16-bit counter
After reset: 00H R/W Address: FFFFF602H
0 7
The 16-bit counter is not cleared to 0000H when its count value matches
value of CCR1 register.
The 16-bit counter is cleared to 0000H when the count after a match between
the 16-bit counter count value and CCR1 register value is a down-count
TT0ECM1
0
1
Control of encoder clear operation 1
The 16-bit counter is not cleared to 0000H when its count value matches
value of CCR0 register.
The 16-bit counter is cleared to 0000H when the count after a match between
the 16-bit counter count value and CCR0 register value is an up-count
TT0ECM0
0
1
Control of encoder clear operation 0
Normal operation
Holds count value of 16-bit counter when TT0CTL0.TT0CE bit = 0.
TT0ECC
0
1
Encoder counter control