Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 439 of 1513
Aug 12, 2011
9.4 Registers
(1) TMT0 control register 0 (TT0CTL0)
The TT0CTL0 register is an 8-bit register that controls the operation of TMT0.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TT0CTL0 register by software.
TT0CE
TMT0 operation disabled (TMT0 reset asynchronously
Note
)
TMT0 operation enabled. TMT0 operation start
TT0CE
0
1
TMT0 operation control
TT0CTL0 0 0 0 0 TT0CKS2 TT0CKS1 TT0CKS0
654321
After reset: 00H R/W Address: FFFF600H
<7> 0
f XX
f XX /2
f
XX /4
f
XX /8
f
XX /16
f
XX /32
f
XX /64
f
XX /128
TT0CKS2
0
0
0
0
1
1
1
1
Internal count clock selection
TT0CKS1
0
0
1
1
0
0
1
1
TT0CKS0
0
1
0
1
0
1
0
1
Note The TT0OPT0.TT0OVF bit and 16-bit counter are reset simultaneously.
Moreover, timer outputs (TOT00 and TOT01) are reset at the same time as the
16-bit counter.
Cautions 1. Set the TT0CKS2 to TT0CKS0 bits when the TT0CE bit = 0.
When the value of the TT0CE bit is changed from 0 to 1, the TT0CKS2
to TT0CKS0 bits can be set simultaneously.
2. Be sure to set bits 3 to 6 to “0”.
Remark f
XX: Peripheral clock