Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 436 of 1513
Aug 12, 2011
Figure 9-1. Block Diagram of TMT0
fXX
fXX/2
fXX/4
f
XX/8
fXX/16
fXX/32
f
XX/64
fXX/128
TT0CNT TT0TCW
TT0CCR0
TT0CCR1
INTTT0OV
INTTT0CC0
TOT00
TOT01
INTTT0CC1
INTTT0EC
TIT01
TIT00
TECR0
EVTT0/TENC00
Note
TENC01
fXX
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
Selector
Internal bus
Internal bus
CCR1
buffer
register
16-bit counter
CCR0
buffer
register
Counter
control
Clear
Selector
Output controller
Sampling
clock
Edge detection/
Noise eliminator
Edge detection/
Noise eliminator
Edge detection/
Noise eliminator
Edge detection/
Noise eliminator
Edge detection/
Noise eliminator
Note Shared with the external trigger input function
Remark f
XX: Peripheral clock