Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 435 of 1513
Aug 12, 2011
9.3 Configuration
TMT0 includes the following hardware.
Table 9-1. Configuration of TMT0
Item Configuration
Registers
16-bit counter × 1
TMT0 capture/compare registers 0, 1 (TT0CCR0, TT0CCR1)
TMT0 counter read buffer register (TT0CNT)
TMT0 counter write register (TT0TCW)
CCR0, CCR1 buffer registers
TMT0 control registers 0, 1 (TT0CTL0, TT0CTL1)
TMT0 control registers 2 (TT0CTL2)
TMT0 I/O control registers 0 to 3 (TT0IOC0 to TT0IOC3)
TMT0 option register 0 (TT0OPT0)
TMT0 option register 1 (TT0OPT1)
TMT noise elimination control register (TTNFC)
Timer input
• TIT00, TIT01 (capture trigger input pins)
• EVTT0/TENC00 (external event input/encoder 0 input pin)
Note
• TENC01 (encoder 1 input pin)
• TENCR0 (encoder clear input pin)
Timer output TOT00, TOT01
Note Shared with the external trigger input function