Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 433 of 1513
Aug 12, 2011
8.7 Cautions
(1) Capture operation
When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be
captured in the TABnCCR0, TABnCCR1, TABnCCR2, and TABnCCR3 registers if the capture trigger is input
immediately after the TABnCE bit is set to 1.
(a) Free-running timer mode
Count clock
0000H
FFFFH
TABnCE bit
TABnCCR0 register
FFFFH 0001H0000H
TIABn0 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX)
Capture
trigger input
(b) Pulse width measurement mode
0000H
FFFFH
FFFFH 0002H0000H
Count clock
TABnCE bit
TABnCCR0 register
TIABn0 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX)
Capture
trigger input
Remark n = 0, 1