Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 427 of 1513
Aug 12, 2011
(1) Operation flow in pulse width measurement mode
Figure 8-37. Software Processing Flow in Pulse Width Measurement Mode
<1> <2>
Set TABnCTL0 register
(TABnCE bit = 1)
TABnCE bit = 0
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits),
TABnCTL1 register,
TABnIOC1 register,
TABnIOC2 register,
TABnOPT0 register
The initial setting of these registers
is performed before setting the
TABnCE bit to 1.
The TABnCKS0 to TABnCKS2 bits can
be set at the same time when counting
has been started (TABnCE bit = 1).
The counter is initialized and counting
is stopped by clearing the TABnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
FFFFH
16-bit counter
0000H
TABnCE bit
TIABn0 pin input
TABnCCR0 register
INTTABnCC0 signal
D00000H 0000HD1 D2