Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 426 of 1513
Aug 12, 2011
Figure 8-36. Register Setting in Pulse Width Measurement Mode (2/2)
(e) TABn option register 0 (TABnOPT0)
00000
TABnOPT0
Overflow flag
0 0 0/1
TABnOVF
TABnCCS0TABnCCS1
TABnCCS2TABnCCS3
(f) TABn counter read buffer register (TABnCNT)
The value of the 16-bit counter can be read by reading the TABnCNT register.
(g) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
These registers store the count value of the 16-bit counter when the valid edge input to the TIABnm pin is
detected.
Remarks 1. TABn I/O control register 0 (TABnIOC0) is not used in the pulse width measurement mode.
2. m = 0 to 3,
n = 0, 1