Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 425 of 1513
Aug 12, 2011
Figure 8-36. Register Setting in Pulse Width Measurement Mode (1/2)
(a) TABn control register 0 (TABnCTL0)
0/1 0 0 0 0
TABnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TABnCKS2 TABnCKS1 TABnCKS0 TABnCE
Note The setting is invalid when the TABnEEE bit = 1.
(b) TABn control register 1 (TABnCTL1)
0 0 0/1 0 0
TABnCTL1
110
TABnMD2 TABnMD1 TABnMD0
1, 1, 0:
Pulse width measurement mode
TABnEEETABnEST
0: Operate on count clock
selected by TABnCKS0 to
TABnCKS2 bits
1: Count by external event
count input signal
(c) TABn I/O control register 1 (TABnIOC1)
0/1 0/1 0/1 0/1 0/1
TABnIOC1
Select valid edge
of TIABn0 pin input
Select valid edge
of TIABn1 pin input
0/1 0/1 0/1
TABnIS2 TABnIS1 TABnIS0TABnIS3
TABnIS6 TABnIS5 TABnIS4TABnIS7
Select valid edge
of TIABn2 pin input
Select valid edge
of TIABn3 pin input
(d) TABn I/O control register 2 (TABnIOC2)
0 0 0 0 0/1
TABnIOC2
0/1 0 0
TABnETS1 TABnETS0
TABnEES0TABnEES1
Select valid edge of
external event count input
Remark n = 0, 1