Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 424 of 1513
Aug 12, 2011
Figure 8-35. Basic Timing in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TABnCE bit
TIABnm pin input
TABnCCRm register
INTTABnCCm signal
INTTABnOV signal
TABnOVF bit
D 0 0000H D 1 D 2 D 3
Cleared to 0 by
CLR instruction
Remark m = 0 to 3,
n = 0, 1
When the TABnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIABnm pin is
later detected, the count value of the 16-bit counter is stored in the TABnCCRm register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTABnCCm) is generated.
The pulse width is calculated as follows.
Pulse width = Captured value × Count clock cycle
If the valid edge is not input to the TIABnm pin even when the 16-bit counter has counted up to FFFFH, an overflow
interrupt request signal (INTTABnOV) is generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TABnOPT0.TABnOVF bit) is also set to 1. Clear the overflow flag to 0
by executing the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H × TABnOVF bit setting (1) count + Captured value) × Count clock cycle
Remark m = 0 to 3,
n = 0, 1