Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 423 of 1513
Aug 12, 2011
8.5.7 Pulse width measurement mode (TABnMD2 to TABnMD0 bits = 110)
In the pulse width measurement mode, TABn starts counting when the TABnCTL0.TABnCE bit is set to 1. Each time
the valid edge input to the TIABnm pin has been detected, the count value of the 16-bit counter is stored in the
TABnCCRm register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TABnCCRm register after a capture interrupt request
signal (INTTABnCCm) occurs.
Select one of the TIABn0 to TIABn3 pins as the capture trigger input pin. Specify “No edge detected” for the unused
pins by using the TABnIOC1 register.
When an external clock is used as the count clock, measure the pulse width of the TIAB0k pin because the external
clock is fixed to the TIAB00 pin. At this time, clear the TAB0IOC1.TAB0IS1 and TAB0IOC1.TAB0IS0 bits to 00 (capture
trigger input (TIAB00 pin): No edge detected).
For TAB1, the external clock is input from the EVTAB1 pin, and the pulse width can be measured by using the TIAB10
to TIAB13 pins.
Remark m = 0 to 3,
n = 0, 1
k = 1 to 3
Figure 8-34. Configuration in Pulse Width Measurement Mode
INTTABnOV signal
INTTABnCC0 signal
INTTABnCC1 signal
INTTABnCC2 signal
INTTABnCC3 signal
TIABn3 pin
(capture
trigger input)
TABnCCR3
register
(capture)
TIAB00 pin
(external event
count input
Note
/
capture
trigger input)
Internal count clock
TABnCE
bit
TIABn1 pin
(capture
trigger input)
TIABn2 pin
(capture
trigger input)
TABnCCR0
register
(capture)
TABnCCR1
register
(capture)
TABnCCR2
register
(capture)
16-bit counter
Clear
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Count
clock
selection
Note TAB1: EVTAB1 pin
Remark n = 0, 1