Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 422 of 1513
Aug 12, 2011
(e) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TABnOVF bit to 0 with the CLR instruction and by writing
8-bit data (bit 0 is 0) to the TABnOPT0 register. To accurately detect an overflow, read the TABnOVF bit when it
is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting)
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TABnOVF bit)
Read Write
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TABnOVF bit)
Read Write
0 write signal
Overflow
set signal
0 write signal
Overflow
set signal
Overflow flag
(TABnOVF bit)
Overflow flag
(TABnOVF bit)
L
H
L
Remark n = 0, 1
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may
be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred
even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set even after execution of the CLR instruction.