Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)

R01UH0042EJ0500 Rev.5.00 Page 421 of 1513

Aug 12, 2011

Example when capture trigger interval is long

FFFFH

16-bit counter

0000H

TABnCE bit

TIABnm pin input

TABnCCRm register

INTTABnOV signal

TABnOVF bit

Overflow counter

Note

1H0H 2H 0H

<1> <2> <3> <4>

1 cycle of 16-bit counter

Pulse width

Note The overflow counter is set arbitrarily by software in the internal RAM.

<1> Read the TABnCCRm register (setting of the default value of the TIABnm pin input).

<2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow

interrupt servicing.

<3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to

0 in the overflow interrupt servicing.

<4> Read the TABnCCRm register.

Read the overflow counter.

When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + D

m1 – Dm0).

In this example, the pulse width is (20000H + D

m1 – Dm0) because an overflow occurs twice.

Clear the overflow counter (0H).

Remark m = 0 to 3,

n = 0, 1