Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 418 of 1513
Aug 12, 2011
(1/2)
Example when two capture registers are used (using overflow interrupt)
FFFFH
16-bit counter
0000H
TABnCE bit
INTTABnOV signal
TABnOVF bit
TABnOVF0 flag
Note
TIABn0 pin input
TABnCCR0 register
TABnOVF1 flag
Note
TIABn1 pin input
TABnCCR1 register
D 10
D 11
D 00
D 01
D 10
<1> <2> <5> <6><3> <4>
D 00
D 11
D 01
Note The TABnOVF0 and TABnOVF1 flags are set in the internal RAM by software.
<1> Read the TABnCCR0 register (setting of the default value of the TIABn0 pin input).
<2> Read the TABnCCR1 register (setting of the default value of the TIABn1 pin input).
<3> An overflow occurs. Set the TABnOVF0 and TABnOVF1 flags to 1 in the overflow interrupt servicing,
and clear the overflow flag to 0.
<4> Read the TABnCCR0 register.
Read the TABnOVF0 flag. If the TABnOVF0 flag is 1, clear it to 0.
Because the TABnOVF0 flag is 1, the pulse width can be calculated by (10000H + D
01 − D00).
<5> Read the TABnCCR1 register.
Read the TABnOVF1 flag. If the TABnOVF1 flag is 1, clear it to 0 (the TABnOVF0 flag is cleared in
<4>, and the TABnOVF1 flag remains 1).
Because the TABnOVF1 flag is 1, the pulse width can be calculated by (10000H + D
11 − D10)
(correct).
<6> Same as <3>