Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 413 of 1513
Aug 12, 2011
(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When TABn is used as an interval timer with the TABnCCRm register used as a compare register, software
processing is necessary for setting a comparison value to generate the next interrupt request signal each time
the INTTABnCCm signal has been detected.
D
00
D
10
D
20
D
01
D
30
D
12
D
03
D
22
D
31
D
21
D
23
D
02
D
13
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
INTTABnCC0 signal
TOABn0 pin output
TABnCCR1 register
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
INTTABnCC3 signal
TOABn3 pin output
Interval period
(D
00
+ 1)
Interval period
(10000H +
D
02
− D
01
)
Interval period
(D
01
− D
00
)
Interval period
(D
03
− D
02
)
Interval period
(D
04
− D
03
)
D
00
D
01
D
02
D
03
D
04
D
05
Interval period
(D
10
+ 1)
Interval period
(10000H + D
12
− D
11
)
Interval period
(D
11
− D
10
)
Interval period
(D
13
− D
12
)
D
10
D
11
D
12
D
13
D
14
Interval period
(D
20
+ 1)
Interval period
(10000H + D
21
− D
20
)
Interval period
(10000H + D
23
− D
22
)
Interval period
(D
22
− D
21
)
Interval period
(D
30
+ 1)
Interval period
(10000H + D
31
− D
30)
D
20
D
21
D
22
D
23
D
31
D
30
D
32
D
04
D
11
Remark n = 0, 1