Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 412 of 1513
Aug 12, 2011
Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)
TABnCE bit = 1
Read TABnOPT0 register
(check overflow flag).
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits),
TABnCTL1 register,
TABnIOC1 register,
TABnOPT0 register
The initial setting of these registers
is performed before setting the
TABnCE bit to 1.
The TABnCKS0 to TABnCKS2 bits can
be set at the same time when counting
has been started (TABnCE bit = 1).
START
Execute instruction to clear
TABnOVF bit (CLR TABnOVF).
<1> Count operation start flow
<2> Overflow flag clear flow
TABnCE bit = 0
The counter is initialized and
counting is stopped by
clearing the TABnCE bit to 0.
STOP
<3> Count operation stop flow
TABnOVF bit = 1
NO
YES
Remark n = 0, 1