Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 411 of 1513
Aug 12, 2011
(b) When using capture/compare register as capture register
Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2)
D 20
D 00
D 30
D 10
D 11
D 21
D 31
D 12 D 01
D 02
D 22
D 32
D 03
D 13
D 33
D 23
0000 D 00 D 01 D 02 D 03 0000
0000
0000
0000
0000 D 10 D 11 D 12 D 13
0000 D 20 D 21 D 23 D 22
0000 D 30 D 31 D 32 D 33
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
<3><1>
<2> <2> <2>
FFFFH
16-bit counter
0000H
TABnCE bit
TIABn2 pin input
TABnCCR2 register
INTTABnCC2 signal
TIABn3 pin input
TABnCCR3 register
INTTABnCC3 signal
INTTABnOV signal
TABnOVF bit
TIABn1 pin input
TABnCCR1 register
INTTABnCC1 signal
TIABn0 pin input
TABnCCR0 register
INTTABnCC0 signal
Remark n = 0, 1