Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)

R01UH0042EJ0500 Rev.5.00 Page 410 of 1513

Aug 12, 2011

Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)

TABnCE bit = 1

Read TABnOPT0 register

(check overflow flag).

TABnCTL0 register

(TABnCKS0 to TABnCKS2 bits),

TABnCTL1 register,

TABnIOC0 register,

TABnIOC2 register,

TABnOPT0 register,

TABnCCR0 to TABnCCR3

registers

The initial setting of these registers

is performed before setting the

TABnCE bit to 1.

The TABnCKS0 to TABnCKS2 bits

can be set at the same time

when counting has been started

(TABnCE bit = 1).

START

Execute instruction to clear

TABnOVF bit (CLR TABnOVF).

<1> Count operation start flow

<2> Overflow flag clear flow

TABnCE bit = 0

The counter is initialized and

counting is stopped by

clearing the TABnCE bit to 0.

STOP

<3> Count operation stop flow

TABnOVF bit = 1

YES

Remark n = 0, 1