Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 408 of 1513
Aug 12, 2011
Figure 8-31. Register Setting in Free-Running Timer Mode (3/3)
(h) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
These registers function as capture registers or compare registers according to the setting of the
TABnOPT0.TABnCCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIABnm pin is detected.
When the registers function as compare registers and when D
m is set to the TABnCCRm register, the
INTTABnCCm signal is generated when the counter reaches (D
m + 1), and the output signal of the
TOABnm pin is inverted.
Remark m = 0 to 3,
n = 0, 1