Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 407 of 1513
Aug 12, 2011
Figure 8-31. Register Setting in Free-Running Timer Mode (2/3)
(d) TABn I/O control register 1 (TABnIOC1)
0/1 0/1 0/1 0/1 0/1
TABnIOC1
Select valid edge
of TIABn0 pin input
Select valid edge
of TIABn1 pin input
0/1 0/1 0/1
TABnIS2 TABnIS1 TABnIS0TABnIS3
TABnIS6 TABnIS5 TABnIS4TABnIS7
Select valid edge
of TIABn2 pin input
Select valid edge
of TIABn3 pin input
(e) TABn I/O control register 2 (TABnIOC2)
0 0 0 0 0/1
TABnIOC2
Select valid edge of
external event count input
0/1 0 0
TABnEES0 TABnETS1 TABnETS0TABnEES1
(f) TABn option register 0 (TABnOPT0)
0/1 0/1 0/1 0/1 0
TABnOPT0
Overflow flag
Specifies if TABnCCR0
register functions as
capture or compare register
Specifies if TABnCCR1
register functions as
capture or compare register
0 0 0/1
TABnCCS0 TABnOVF TABnCCS1
TABnCCS2TABnCCS3
Specifies if TABnCCR2
register functions as
capture or compare register
Specifies if TABnCCR3
register functions as
capture or compare register
(g) TABn counter read buffer register (TABnCNT)
The value of the 16-bit counter can be read by reading the TABnCNT register.
Remark n = 0, 1