Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 406 of 1513
Aug 12, 2011
Figure 8-31. Register Setting in Free-Running Timer Mode (1/3)
(a) TABn control register 0 (TABnCTL0)
0/1 0 0 0 0
TABnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TABnCKS2 TABnCKS1 TABnCKS0 TABnCE
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1
(b) TABn control register 1 (TABnCTL1)
0 0 0/1 0 0
TABnCTL1
101
TABnMD2 TABnMD1 TABnMD0TABnEEETABnESTTABnSYE
1, 0, 1:
Free-running mode
0: Operate with count
clock selected by
TABnCKS0 to TABnCKS2 bits
1: Count by external
event count input signal
(c) TABn I/O control register 0 (TABnIOC0)
0/1 0/1 0/1 0/1 0/1
TABnIOC0
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Setting of output level with
operation of TOABn1 pin
disabled
0: Low level
1: High level
0/1 0/1 0/1
TABnOE1 TABnOL0 TABnOE0TABnOL1
TABnOE3 TABnOL2 TABnOE2TABnOL3
Setting of output level with
operation of TOABn3 pin
disabled
0: Low level
1: High level
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Setting of output level with
operation of TOABn2 pin
disabled
0: Low level
1: High level
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Setting of output level with
operation of TOABn0 pin disabled
0: Low level
1: High level
Remark n = 0, 1