Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 405 of 1513
Aug 12, 2011
When the TABnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIABnm pin is
detected, the count value of the 16-bit counter is stored in the TABnCCRm register, and a capture interrupt request signal
(INTTABnCCm) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTABnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TABnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction
by software.
Remark m = 0 to 3,
n = 0, 1
Figure 8-30. Basic Timing in Free-Running Timer Mode (Capture Function)
D 20
D 00
D 30
D 10
D 11
D 21
D 31
D 12 D 01
D 02
D 22
D 32
D 03
D 13
D 33
D 23
0000 D 00 D 01 D 02 D 03
0000 D 10 D 11 D 12 D 13
0000 D 20 D 21 D 23 D 22
0000 D 30 D 31 D 32 D 33
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
FFFFH
16-bit counter
0000H
TIABn2 pin input
TABnCCR2 register
INTTABnCC2 signal
TIABn3 pin input
TABnCCR3 register
INTTABnCC3 signal
INTTABnOV signal
TABnOVF bit
TIABn1 pin input
TABnCCR1 register
INTTABnCC1 signal
TABnCE bit
TIABn0 pin input
TABnCCR0 register
INTTABnCC0 signal