Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 404 of 1513
Aug 12, 2011
When the TABnCE bit is set to 1, TABn starts counting, and the output signals of the TOABn0 to TOABn3 pins are
inverted. When the count value of the 16-bit counter subsequently matches the set value of the TABnCCRm register, a
compare match interrupt request signal (INTTABnCCm) is generated, and the output signal of the TOABnm pin is inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTABnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TABnOPT0.TABnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR
instruction by software.
The TABnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
that time, and compared with the count value.
Remark m = 0 to 3,
n = 0, 1
Figure 8-29. Basic Timing in Free-Running Timer Mode (Compare Function)
D 10
D 20
D 30
D 00
D 20 D 31 D 31
D 30
D 00
D 11 D 11
D 21
D 01
D 11
D 21
D 01
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
FFFFH
16-bit counter
0000H
TOABn1 pin output
TABnCCR2 register
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
INTTABnCC3 signal
TOABn3 pin output
INTTABnOV signal
TABnOVF bit
TOABn0 pin output
TABnCCR1 register
INTTABnCC1 signal
TABnCE bit
TABnCCR0 register
INTTABnCC0 signal
D 00 D 01
D 11 D 10
D 21 D 20
D 31 D 30