Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 403 of 1513
Aug 12, 2011
8.5.6 Free-running timer mode (TABnMD2 to TABnMD0 bits = 101)
In the free-running timer mode, TABn starts counting when the TABnCTL0.TABnCE bit is set to 1. At this time, the
TABnCCRm register can be used as a compare register or a capture register, according to the setting of the
TABnOPT0.TABnCCS0 and TABnOPT0.TABnCCS1 bits.
Remark m = 0 to 3,
n = 0, 1
Figure 8-28. Configuration in Free-Running Timer Mode
TOABn3 pin output
TOABn2 pin output
TOABn1 pin output
TOABn0 pin output
INTTABnOV signal
TABnCCS0,
TABnCCS1 bits
(capture/compare
selection)
INTTABnCC3 signal
INTTABnCC2 signal
INTTABnCC1 signal
INTTABnCC0 signal
TIABn3 pin
(capture
trigger input)
TABnCCR3
register
(capture)
TIAB00 pin
(external event
count input
Note
/
capture
trigger input)
Internal count clock
TABnCE
bit
TIABn1 pin
(capture
trigger input)
TIABn2 pin
(capture
trigger input)
TABnCCR0
register
(capture)
TABnCCR1
register
(capture)
TABnCCR2
register
(capture)
TABnCCR3
register
(compare)
TABnCCR2
register
(compare)
TABnCCR1
register
(compare)
0
1
0
1
0
1
0
1
16-bit counter
TABnCCR0
register
(compare)
Output
controller
Output
controller
Output
controller
Output
controller
Count
clock
selection
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Note TAB1: EVTAB1 pin