Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 401 of 1513
Aug 12, 2011
(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TABnCCRk register to 0000H. If the set value of the TABnCCR0 register is
FFFFH, the INTTABnCCk signal is generated periodically.
Count clock
16-bit counter
TABnCE bit
TABnCCR0 register
TABnCCRk register
INTTABnCC0 signal
INTTABnCCk signal
TOABnk pin output
D 0
0000H
D
0
0000H
D
0
0000H
D 0 − 1D 0 0000FFFF 0000 D 0 − 1D 0 00000001
L
Remark k = 1 to 3,
n = 0, 1
To output a 100% waveform, set a value of “set value of TABnCCR0 register + 1” to the TABnCCRk register. If
the set value of the TABnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
TABnCE bit
TABnCCR0 register
TABnCCRk register
INTTABnCC0 signal
INTTABnCCk signal
TOABnk pin output
D0
D0 + 1
D
0
D0 + 1
D
0
D0 + 1
D0 − 1D00000FFFF 0000 D0 − 1D0 00000001
Remark k = 1 to 3,
n = 0, 1