Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 398 of 1513
Aug 12, 2011
Figure 8-27. Software Processing Flow in PWM Output Mode (2/2)
START
<1> Count operation start flow
TABnCE bit = 1
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2
bits),
TABnCTL1 register,
TABnIOC0 register,
TABnIOC2 register,
TABnCCR0 to TABnCCR3
registers
The initial setting of these
registers is performed
before setting the
TABnCE bit to 1.
Writing the TABnCCR1 register
must be performed only when
the set duty factor is changed
after writing the TABnCCR2 and
TABnCCR3 registers.
When the counter is cleared after
setting, the value of the
TABnCCRm register is transferred
to the CCRm buffer register.
Writing the same value to the
TABnCCR1 register is necessary
only when the set duty factor of
TOABn2 and TOABn3 pin
outputs is changed.
When the counter is
cleared after setting,
the value of the TABnCCRm
register is transferred to
the CCRm buffer register.
The TABnCCR1 register only needs
to be written, only when the set duty
factor is changed.
When the counter is cleared after
setting, the value of the TABnCCRm
register is transferred to the CCRm
buffer register.
Counting is stopped.
The TABnCKS0 to
TABnCKS2 bits can be
set at the same time
when counting is
enabled (TABnCE bit = 1).
Writing the TABnCCR1
register must be performed
after writing the TABnCCR0,
TABnCCR2, and TABnCCR3
registers.
When the counter is cleared
after setting, the value
of the TABnCCRm register is
transferred to the CCRm buffer
registers.
Writing the same value
to TABnCCR1 is
necessary only when the
set cycle is changed.
<2> TABnCCR0 to TABnCCR3 register
setting change flow
<3> TABnCCR0 register setting change flow
<4> TABnCCR1 to TABnCCR3 register
setting change flow
<5> TABnCCR2, TABnCCR3 register
setting change flow
<6> TABnCCR1 register setting change flow
<7> Count operation stop flow
TABnCE bit = 0
Setting of TABnCCR2,
TABnCCR3 registers
Setting of TABnCCR1 register
Setting of TABnCCR2,
TABnCCR3 registers
Setting of TABnCCR1 register
STOP
Setting of TABnCCR1 register
Setting of TABnCCR0 register
Setting of TABnCCR1 register
Setting of TABnCCR0, TABnCCR2,
and TABnCCR3 registers
Setting of TABnCCR1 register
When the counter is
cleared after setting, the
value of the TABnCCRm
register is transferred to
the CCRm buffer register.
Remark k = 1 to 3,
m = 0 to 3,
n = 0, 1