Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 396 of 1513
Aug 12, 2011
Figure 8-26. Register Setting in PWM Output Mode (3/3)
(f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
If D
0 is set to the TABnCCR0 register and Dk to the TABnCCRk register, the cycle and active level of the
PWM waveform are as follows.
Cycle = (D
0 + 1) × Count clock cycle
Active level width = D
k × Count clock cycle
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not
used in the PWM output mode.
2. Updating TABn capture/compare register 2 (TABnCCR2) and TABn capture/compare register
3 (TABnCCR3) is enabled by writing TABn capture/compare register 1 (TABnCCR1).
3. n = 0, 1