Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 394 of 1513
Aug 12, 2011
When the TABnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
PWM waveform from the TOABnk pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TABnCCRk register) × Count clock cycle
Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TABnCCRk register)/(Set value of TABnCCR0 register + 1)
The PWM waveform can be changed by rewriting the TABnCCRm register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
The compare match interrupt request signal (INTTABnCC0) is generated when the 16-bit counter counts up next time
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal (INTTABnCCk) is generated when the count value of the 16-bit counter matches
the value of the CCRk buffer register.
Remark k = 1 to 3,
m = 0 to 3,
n = 0, 1
Figure 8-26. Setting of Registers in PWM Output Mode (1/3)
(a) TABn control register 0 (TABnCTL0)
0/1 0 0 0 0
TABnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TABnCKS2 TABnCKS1 TABnCKS0 TABnCE
(b) TABn control register 1 (TABnCTL1)
0 0 0/1 0 0
TABnCTL1
100
TABnMD2 TABnMD1 TABnMD0TABnEEETABnESTTABnSYE
1, 0, 0:
PWM output mode
0: Operate on count clock
selected by TABnCKS0 to
TABnCKS2 bits
1: Count by external event
count input signal
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark n = 0, 1