Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 393 of 1513
Aug 12, 2011
Figure 8-25. Basic Timing in PWM Output Mode
D0
D1
D2
D3
D1
D2
D3
D0D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
INTTABnCC0 signal
TOABn0 pin output
TABnCCR1 register
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
INTTABnCC3 signal
TOABn3 pin output
Active level
width (D
3)
Cycle (D
0 + 1) Cycle (D0 + 1) Cycle (D0 + 1) Cycle (D0 + 1)
Active level
width (D
3)
Active level
width (D3)
Active level
width (D3)
Active
level width
(D
1)
Active
level width
(D
1)
Active
level width
(D
1)
Active
level width
(D
1)
Active
level width
(D
2)
Active
level width
(D
2)
Active
level width
(D
2)
Active
level width
(D
2)
Remark n = 0, 1