Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 392 of 1513
Aug 12, 2011
8.5.5 PWM output mode (TABnMD2 to TABnMD0 bits = 100)
In the PWM output mode, a PWM waveform is output from the TOABn1 to TOABn3 pins when the TABnCTL0.TABnCE
bit is set to 1.
In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOABn0 pin.
Figure 8-24. Configuration in PWM Output Mode
CCR0 buffer register
TABnCE bit
TABnCCR0 register
Clear
Match signal
INTTABnCC0 signal
TOABn3 pin
INTTABnCC3 signal
TOABn0 pin
Transfer
S
R
TABnCCR1
register
CCR1 buffer
register
Match signal
TOABn1 pin
INTTABnCC1 signal
Transfer
Transfer
S
R
TABnCCR3
register
CCR3 buffer
register
Match signal
Transfer
TOABn2 pin
INTTABnCC2 signal
S
R
TABnCCR2
register
CCR2 buffer
register
Match signal
16-bit counter
Count
clock
selection
Output
controller
(RS-FF)
Output
controller
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Remark n = 0, 1