Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 391 of 1513
Aug 12, 2011
(b) Generation timing of compare match interrupt request signal (INTTABnCCk)
The generation timing of the INTTABnCCk signal in the one-shot pulse output mode is different from other
INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit counter matches
the value of the TABnCCRk register.
Count clock
16-bit counter
TABnCCRk register
TOABnk pin output
INTTABnCCk signal
D
k
D
k
− 2D
k
− 1D
k
D
k
+ 1 D
k
+ 2
Usually, the INTTABnCCk signal is generated when the 16-bit counter counts up next time after its count value
matches the value of the TABnCCRk register.
In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is
changed to match the change timing of the TOABnk pin.
Remark k = 1 to 3,
n = 0, 1