Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 390 of 1513
Aug 12, 2011
(2) Operation timing in one-shot pulse output mode
(a) Notes on rewriting TABnCCRm register
To change the set value of the TABnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
D k0
D k1
D 01
D 01 D 00
D k1
D 01
D k0
D k0 D k1
D 00 D 00
FFFFH
16-bit counter
0000H
TABnCE bit
External trigger input
(TIAB00 pin input)
Note
TABnCCR0 register
INTTABnCC0 signal
TOABn0 pin output
(only when software
trigger is used)
TABnCCRk register
INTTABnCCk signal
TOABnk pin output
Delay
(D
k0 )
Active level width
(D
00 − D k0 + 1)
Active level width
(D 01 − D k1 + 1)
Active level width
(D 01 − D k1 + 1)
Delay
(D
k1 )
Delay
(10000H + D k1 )
Note TAB1: TRGAB1 pin
When the TABnCCR0 register is rewritten from D
00 to D01 and the TABnCCRk register from Dk0 to Dk1 where
D
00 > D01 and Dk0 > Dk1, if the TABnCCRk register is rewritten when the count value of the 16-bit counter is
greater than D
k1 and less than Dk0 and if the TABnCCR0 register is rewritten when the count value is greater
than D
01 and less than D00, each set value is reflected as soon as the register has been rewritten and
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
k1, the counter generates the INTTABnCCk signal and asserts the TOABnk
pin. When the count value matches D01, the counter generates the INTTABnCC0 signal, deasserts the
TOABnk pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.
Remark k = 1 to 3,
n = 0, 1