Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 2 PIN FUNCTIONS
R01UH0042EJ0500 Rev.5.00 Page 39 of 1513
Aug 12, 2011
(2/9)
Pin No. Pin Name I/O Function Alternate Function
JG3-H JH3-H
ANI0 P70 100 128
ANI1 P71 99 127
ANI2 P72 98 126
ANI3 P73 97 125
ANI4 P74 96 124
ANI5 P75 95 123
ANI6 P76 94 122
ANI7 P77 93 121
ANI8 P78 92 120
ANI9 P79 91 119
ANI10 P710 90 118
ANI11
Input Analog voltage input for A/D converter
P711 89 117
ANO0 P10 3 3
ANO1
Output Analog voltage output for D/A converter
P11 4 4
ASCKC0 Input UARTC0 baud rate clock input. 5 V tolerant. P32/SCKF4/TIAA00/TOAA00 27 39
P62/TOAB1T2/TIAB12/TOAB12 67
−
ASTB Output Address strobe signal for external memory
PCT6
−
88
AVREF0
−
Reference voltage input for A/D
converter/positive power supply for port 7
−
1 1
AVREF1
−
Reference voltage input for D/A
converter/positive power supply for port 1
−
5 5
AVSS
−
Ground potential for A/D and D/A converters
−
2 2
CLKOUT Output Internal system clock output PCM1 64 86
CRXD0
Note
Input CAN receive data input. 5 V tolerant. P37/RXDC3/SDA00/UDMAAK0 32 44
P63/TOAB1B2/TRGAB1 68
−
CS0 Output Chip select output
PCS0
−
96
P64/TOAB1T3/TIAB13/TOAB13 69
−
CS2 Output Chip select output
PCS2
−
97
P65/TOAB1B3/EVTAB1 70
−
CS3 Output Chip select output
PCS3
−
116
CTXD0
Note
Output CAN transmit data output. 5 V tolerant. P36/TXDC3/SCL00/UDMARQ0 31 43
P54/SOF2/KR4/RTP04 39
−
DCK Input Clock input for on-chip debugging
5 V tolerant
− −
51
P52/TIAB03/KR2/TOAB03/RTP02 37
−
DDI Input Data input for on-chip debugging
5 V tolerant
− −
49
P53/SIF2/TIAB00/KR3/TOAB00/RTP03 38
−
DDO Output Data output for on-chip debugging
In the on-chip debug mode, high-level output is
forcibly set. 5 V tolerant.
− −
50
P55/SCKF2/KR5/RTP05 40
−
DMS Input Mode select signal input for on-chip debugging
5 V tolerant
− −
52
P56/INTP05 41
−
DRST Input Reset signal input for on-chip debugging
5 V tolerant
− −
53
Note μ PD70F3770, 70F3771 only
Remark JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H