Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 389 of 1513
Aug 12, 2011
Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2)
TABnCE bit = 1
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits),
TABnCTL1 register,
TABnIOC0 register,
TABnIOC2 register,
TABnCCR0 to TABnCCR3 registers
The initial setting of these
registers is performed
before setting the
TABnCE bit to 1.
The TABnCKS0 to
TABnCKS2 bits can be
set at the same time
when counting has been
started (TABnCE bit = 1).
Trigger wait status
START
<1> Count operation start flow
TABnCE bit = 0
Count operation is
stopped
STOP
<3> Count operation stop flow
Setting of TABnCCR0 to
TABnCCR3 registers
As rewriting the
TABnCCRm register
immediately sends the
data to the CCRm
buffer register, rewriting
immediately after
the generation of the
INTTABnCCR0 signal
is recommended.
<2> TABnCCR0 to TABnCCR3 register setting change flow
Remark m = 0 to 3,
n = 0, 1