Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 387 of 1513
Aug 12, 2011
Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (3/3)
(f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
If D
0 is set to the TABnCCR0 register and Dk to the TABnCCRk register, the active level width and output
delay period of the one-shot pulse are as follows.
Active level width = (D
0 − Dk + 1) × Count clock cycle
Output delay period = (D
k) × Count clock cycle
Caution One-shot pulses are not output even in the one-shot pulse output mode, if the set
value of the TABnCCRk register is greater than that value of the TABnCCR0 register.
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not
used in the one-shot pulse output mode.
2. k = 1 to 3,
n = 0, 1