Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 385 of 1513
Aug 12, 2011
When the TABnCE bit is set to 1, TABn waits for a trigger. When the trigger is generated, the 16-bit counter is cleared
from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOABnk pin. After the one-shot pulse is
output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the
one-shot pulse is being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TABnCCRk register) × Count clock cycle
Active level width = (Set value of TABnCCR0 register − Set value of TABnCCRk register + 1) × Count clock cycle
The compare match interrupt request signal INTTABnCC0 is generated when the 16-bit counter counts up after its
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTABnCCk) is
generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
The valid edge of the external trigger input or setting the software trigger (TABnCTL1.TABnEST bit) to 1 is used as the
trigger.
Remark k = 1 to 3,
n = 0, 1
Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (1/3)
(a) TABn control register 0 (TABnCTL0)
0/1 0 0 0 0
TABnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TABnCKS2 TABnCKS1 TABnCKS0 TABnCE
(b) TABn control register 1 (TABnCTL1)
0 0/1 0/1 0 0
TABnCTL1
Generate software trigger
when 1 is written
011
TABnMD2 TABnMD1 TABnMD0TABnEST
0, 1, 1:
One-shot pulse output mode
TABnEEETABnSYE
0: Operate on count clock
selected by TABnCKS0 to
TABnCKS2 bits
1: Count by external event
count input signal
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark n = 0, 1