Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 384 of 1513
Aug 12, 2011
Figure 8-21. Basic Timing in One-Shot Pulse Output Mode
D 0
D 1
D 2
D 3
D 1
D 2
D 3
D 0
D 1
D 2
D 3
D 0
D 1
D 2
D 3
D 0
Delay
(D
1 )
Active
level width
(D
0 − D 1 + 1)
Delay
(D
1 )
Active
level width
(D
0 − D 1 + 1)
Delay
(D
1 )
Active
level width
(D
0 − D 1 + 1)
Delay
(D
2 )
Active
level width
(D
0 − D 2 + 1)
Delay
(D
2 )
Active
level width
(D
0 − D 2 + 1)
Delay
(D
2 )
Active
level width
(D
0 − D 2 + 1)
Delay
(D
3 )
Active
level width
(D
0 − D 3 + 1)
Delay
(D
3 )
Active
level width
(D
0 − D 3 + 1)
Delay
(D
3 )
Active
level width
(D
0 − D 3 + 1)
FFFFH
16-bit counter
0000H
TABnCE bit
External trigger input
(TIAB00 pin input)
Note
TABnCCR0 register
INTTABnCC0 signal
TABnCCR2 register
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
INTTABnCC3 signal
TOABn3 pin output
TABnCCR1 register
INTTABnCC1 signal
TOABn1 pin output
TOABn0 pin output
(only when software
trigger is used)
Note TAB1: TRGAB1 pin
Remark n = 0, 1