Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 383 of 1513
Aug 12, 2011
8.5.4 One-shot pulse output mode (TABnMD2 to TABnMD0 bits = 011)
In the one-shot pulse output mode, TABn waits for a trigger when the TABnCTL0.TABnCE bit is set to 1. When the valid
edge of the external trigger input is detected, TABn starts counting, and outputs a one-shot pulse from the TOABn1 to
TOABn3 pins.
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger
is used, the TOABn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the
counter is stopped (waiting for a trigger).
Figure 8-20. Configuration in One-Shot Pulse Output Mode
CCR0 buffer register
TABnCE bit
TABnCCR0 register
Clear
Match signal
INTTABnCC0 signal
TOABn3 pin
INTTABnCC3 signal
TOABn0 pin
TIAB00 pin
Note
Transfer
S
R
S
R
TABnCCR1
register
CCR1 buffer
register
Match signal
TOABn1 pin
INTTABnCC1 signal
Transfer
Transfer
S
R
TABnCCR3
register
CCR3 buffer
register
Match signal
Transfer
TOABn2 pin
INTTABnCC2 signal
S
R
TABnCCR2
register
CCR2 buffer
register
Match signal
16-bit counter
Count clock
selection
Count start
control
Edge
detector
Software trigger
generation
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Note TAB1: TRGAB1 pin
Remark n = 0, 1