Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
R01UH0042EJ0500 Rev.5.00 Page 382 of 1513
Aug 12, 2011
(e) Generation timing of compare match interrupt request signal (INTTABnCCk)
The timing of generation of the INTTABnCCk signal in the external trigger pulse output mode differs from the
timing of other INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit
counter matches the value of the CCRk buffer register.
Count clock
16-bit counter
CCRk buffer register
TOABnk pin output
INTTABnCCk signal
Dk
Dk − 2Dk − 1Dk Dk + 1 Dk + 2
Remark k = 1 to 3,
n = 0, 1
Usually, the INTTABnCCk signal is generated in synchronization with the next count-up after the count value of
the 16-bit counter matches the value of the CCRk buffer register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing
is changed to match the timing of changing the output signal of the TOABnk pin.